ASIC Development is incredibly costly. Partly, because everyone uses the ridiculously expensive tools from the usual "Big3-Mafia". So each time you buy an IP, you are also covering the tool costs of original developer.
This (what seems to be crazy) idea is simple - make a set of tools for an internal use. Much of the big complexity for these tools comes from the fact, that they should be "user friendly" and well documented. If you are making a tool for yourself, you can somewhat cheat on those things, making tools a completely command line intefaced. The resulting gain of using such tools will provide a serious competitive advantage in the market, enabling us to develop IP-blocks at a lower price tag.
Initial planned toolset is following:
1. New high-level HDL 2. Simulator and debugging environment. 3. Synthesis tool (to Verilog RTL)